An LCD has the advantages of portability, low power consumption, and low radiation. Therefore, the LCD has been widely used in various portable information products, such as notebooks, personal digital assistant (PDA), video cameras, and the like.
In general, an LCD includes a gate driver and a data driver. The gate and data drivers drive thin film transistors (TFTs) of an LCD panel of the LCD to display images. Each of the gate and data drivers includes a shift register having a plurality of shift register units connected one by one. Each of the shift register units includes an input terminal and an output terminal. The input terminal of each shift register unit is connected to the output terminal of a pre-stage shift register unit. The output terminal of each shift register unit is connected to the input terminal of a rear-stage shift register unit.
FIG. 6 is a circuit diagram of a shift register unit of a conventional shift register. The shift register unit 100 includes an input terminal (not labeled), a first clock reversed phase circuit 110, a switch circuit 120, a second clock reversed phase circuit 130, and an output terminal (not labeled).
The first clock reversed phase circuit 110 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The first to fourth transistors M1˜M4 are P-channel metal-oxide-semiconductor (PMOS) transistors. A gate electrode of the first transistor M1 is the input terminal of the shift register unit 100 and is used to receive an input signal VS (i.e. an output signal of the output terminal of a pre-stage shift register unit). A source electrode of the first transistor M1 is used to receive a high level signal VDD. A drain electrode of the first transistor M1 is connected to a source electrode of the second transistor M2. A gate electrode and a drain electrode of the second transistor M2 are all used to receive a low level signal VSS. A gate electrode of the third transistor M3 and a gate electrode of the fourth transistor M4 are all used to receive a reverse clock signal CKB. A source electrode of the third transistor M3 is connected to the drain electrode of the first transistor M1. A source electrode of the fourth transistor M4 is connected to the gate electrode of the first transistor M1.
The switch circuit 120 includes a fifth transistor M5 and a sixth transistor M6. The fifth and sixth transistors M5, M6 are PMOS transistors. A gate electrode of the fifth transistor M5 is connected to a drain electrode of the third transistor M3. A source electrode of the fifth transistor M5 is used to receive the high level signal VDD. A drain electrode of the fifth transistor M5 is connected to a source electrode of the sixth transistor M6. A gate electrode of the sixth transistor M6 is connected to a drain electrode of the fourth transistor M4. A drain electrode of the sixth transistor M6 is used to receive the low level signal VSS. The source electrode of the sixth transistor M6 is the output terminal of the shift register unit 100 and is used to output an output signal VO.
The second clock reversed phase circuit 130 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The seventh to tenth transistors M7˜M10 are PMOS transistors. A gate electrode of the seventh transistor M7 is connected to the output terminal. A source electrode of the seventh transistor M7 is used to receive the high level signal VDD. A drain electrode of the seventh transistor M7 is connected to a source electrode of the eighth transistor M8. A drain electrode and a gate electrode of the eighth transistor M8 are all used to receive the low level signal VSS. A source electrode of the ninth transistor M9 is connected to the drain electrode of the third transistor M3. A gate electrode of the ninth transistor M9 is used to receive a clock signal CK. A drain electrode of the ninth transistor M9 is connected to the drain electrode of the seventh transistor M7. A gate electrode of the tenth transistor M10 is used to receive the clock signal CK. A source electrode of the tenth transistor M10 is connected to the drain electrode of the fourth transistor M4. A drain electrode of the tenth transistor M10 is connected to the output terminal.
FIG. 7 is a sequence waveform diagram of pulse signals of the shift register unit of FIG. 5. During a first period T1, the reverse clock signal CKB is a high level, thus the third transistor M3 and the fourth transistor M4 are turned off. The clock signal CK is a low level, thus the ninth transistor M9 and the tenth transistor M10 are turned on. The output signal VO is a high level, thus the output signal VO turns off the sixth transistor M6 via the actived tenth transistor M10. The gate electrode of the eighth transistor M8 receives the low level signal VSS, thus the eighth transistor M8 is turned on. The low level signal VSS turns on the fifth transistor M5 via the actived eighth transistor M8 and the actived ninth transistor M9. The output terminal of the shift register unit 100 receives the high level signal VDD via the actived fifth transistor M5. That is, the output signal VO is high level during the first period T1.
During a second period T2, the reversed clock signal CKB is a low level, thus the third transistor M3 and the fourth transistor M4 are turned on. The clock signal CK is a high level, thus the ninth transistor M9 and the tenth transistor M10 are turned off. The input signal VS is a low level, thus the first transistor M1 is turned on. The high level signal VDD turns off the fifth transistor M5 via the actived first transistor M1 and the actived third transistor M3. The input signal VS turns on the sixth transistor M6 via the actived fourth transistor M4. The output terminal of the shift register unit 100 receives the low level signal VSS via the actived sixth transistor M6. That is, the output signal VO is low level during the second period T2.
During a third period T3, the reversed clock signal CKB is a high level, thus the third transistor M3 and the fourth transistor M4 are turned off. The clock signal CK is a low level, thus the ninth transistor M9 and the tenth transistor M10 are turned on. The output signal VO is a low level, thus the output signal VO turns on the seventh transistor M7 and the sixth transistor M6 via the actived tenth transistor M10. The high level signal VDD turns off the fifth transistor M5 via the actived seventh transistor M7 and the actived ninth transistor M9. The output terminal of the shift register unit 100 receives the low level signal VSS via the actived sixth transistor M6. That is, the output signal VO is low level during the third period T3.
During a fourth period T4, the reversed clock signal CKB is a low level, thus the third transistor M3 and the fourth transistor M4 are turned on. The clock signal CK is a high level, thus the ninth transistor M9 and the tenth transistor M10 are turned off. The input signal VS is high level, thus the first transistor M1 is turned off. The input signal VS turns off the sixth transistor M6 via the actived fourth transistor M4. The gate electrode of the second transistor M2 receives the low level signal VSS, thus the second transistor M2 is turned on. The low level signal VSS turns on the fifth transistor M5 via the actived second transistor M2 and the actived third transistor M3. The output terminal of the shift register unit 100 receives the high level signal VDD via the actived fifth transistor M5. That is, the output signal VO is high level during the fourth period T4.
During the first period T1, the first transistor M1 and the second transistor M2 are turned on, thus, the first transistor M1 and the second transistor M2 form a current path to conduct the high level signal VDD and the low level signal VSS. During the second period T2, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned on. The first transistor M1 and the second transistor M2 form a first current path to current path to conduct the high level signal VDD and the low level signal VSS. The fifth transistor M5 and the sixth transistor M6 form a second current path to conduct the high level signal VDD and the low level signal VSS. The seventh transistor M7 and the eighth transistor M8 form a third current path to conduct the high level signal VDD and the low level signal VSS. During the third period T3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned on. The fifth transistor M5 and the sixth transistor M6 form a first current path to conduct the high level signal VDD and the low level signal VSS. The seventh transistor M7 and the eighth transistor M8 form a second current path to conduct the high level signal VDD and the low level signal VSS. During most of the operating time of the shift register, the high level signal VDD and the low level signal VSS are conducted. A voltage difference between the high level signal VDD and the low level signal VSS is large, a conductive resistance of a drain electrode and a source electrode of a transistor is small, thus, current flowing through the current paths is large. A power consumption of the shift register is correspondingly large. When the gate driver or the source driver of the LCD employs the shift register, a power consumption of the LCD is correspondingly large.
What is needed, therefore, is a shift register and an LCD employing the shift register that can overcome the above-described deficiencies.